1. Field of the Invention
This invention relates to integrated circuit packaging technology, and more particularly, to a new flip-chip technology, denominated as DDFC (Direct-Downset Flip-Chip) technology, which can be used to fabricate a flip-chip package without the necessity of solder-deflux and flip-chip underfill steps.
2. Description of Related Art
Flip-chip technology is an advanced integrated circuit packaging technology, which is characterized by that the packaged semiconductor chip is mounted in an upside-down manner (i.e., flip chip) over a substrate and mechanically bonded and electrically coupled to the same by means of solder bumps. A typical flip-chip package assembly and method of fabricating the same is illustratively depicted in the following with reference to FIGS. 1A-1C and FIG. 2.
Referring first to FIG. 1A, this conventional flip-chip technology is used to pack a semiconductor chip 10 over a substrate 20 (note that FIGS. 1A-1C are simplified schematic diagrams to show only a small number of I/O pads and the parts related to the invention; the actual layout of the flip-chip package assembly may be much more complex; and some component sizes are enlarged for the purpose of easy understanding).
The semiconductor chip 10 has a circuit surface 10a (or called active surface, which is the surface where active circuit components and I/O pads are fabricated) and a noncircuit surface 10b (or called inactive surface, which is the surface where no active circuit components and I/O pads are fabricated). The circuit surface 10a of the semiconductor chip 10 is formed with an array of I/O pads 11, on which an array of solder bumps 30 are attached through a bumping process.
The substrate 20 has a front surface 20a and a back surface 20b, with the front surface 20a thereof being a flat plane and provided with an array of flatly-shaped solder-bump pads 21 arranged in correspondence to the array of solder bumps 30 over the circuit surface 10a of semiconductor chip 10. These solder-bump pads 21 which are each connected to one of a plurality of electrically-conductive traces (not shown) on the substrate 20.
As shown in FIG. 2, the conventional flip-chip packaging process with the semiconductor chip 10 and the substrate 20 includes the following five essential steps
(S1) Die Bonding (D/B);
(S2) Solder Reflow;
(S3) Solder Deflux;
(S4) Flip-Chip Underfill; and
(S5) Solder Ball (S/B).
Referring to FIG. 1B, in the die bonding step (step S1), the semiconductor chip 10 is mounted on the front surface 20a of the substrate 20, with the array of solder bumps 30 on the circuit surface 10a of the semiconductor chip 10 being aligned and attached respectively to the array of solder-bump pads 21 on the front surface 20a of the substrate 20.
As the semiconductor chip 10 is mounted in position over the substrate 20, a solder-reflow step (step S2) is performed to reflow the solder bumps 30 over the solder-bump pads 21, so as to cause the solder bumps 30 to be wetted to the solder-bump pads 21, thereby mechanically bonding and electrically coupling the semiconductor chip 10 to the substrate 20.
During the foregoing solder-reflow process, however, some solder fluxes would be left over other areas beyond the solder-bump pads 21. Therefore, in subsequence to the solder-reflow process, it is required to perform a solder-deflux step (step S3) so as to clean away the remanant solder fluxes over the substrate 20.
As the semiconductor chip 10 is bonded in position, however, a gap 12 would be undesirably left under the semiconductor chip 10 (i.e., between the semiconductor chip 10 and the substrate 20). Since the semiconductor chip 10 is different in coefficient of thermal expansion (CTE) from the substrate 20, if the gap 12 is not underfilled, it would easily cause the overall package construction to suffer from fatigue cracking and electrical failure due to thermal stress when undergoing high-temperature conditions.
Referring further to FIG. 1C, as a solution to the above-mentioned problem, it is required to perform a flip-chip underfill step (step S4) to fill an underfill material, such as epoxy resin, into the gap 12 shown in FIG. 1B to thereby form an underfill layer 13 between the semiconductor chip 10 and the substrate 20. The underfilled resin, when hardened, can serve as a mechanical reinforcement to the semiconductor chip 10 to cope against thermal stress.
Presently, a great variety of flip-chip underfill methods are available for the fabrication of the underfill layer 13. However, most of these flip-chip underfill methods are quite complex in procedural steps and thus laborious and time-consuming to implement.
Finally, a solder-ball implantation step (step S5) is performed to implant an array of solder balls 40 over the back surface 20b of the substrate 20, which are electrically connected to the electrically-conductive traces (not shown) connected to the solder-bump pads 21 to serve as external connecting means for the flip-chip packaged. This completes the flip-chip packaging process.
In practical implementation, however, the foregoing conventional flip-chip technology has the following drawbacks.
First, both the solder-deflux process (step S3) and the flip-chip underfill process (step S4) are quite laborious and time-consuming to implement, making the overall flip-chip packaging process quite cost-ineffective.
Second, since the solder-bump pads 21 are quite small in size, they provide only a small solder-wetting area for wetting to the solder bumps 30; and therefore, the wetting of the solder bumps 30 over the solder-bump pads 21 would be critical and thus likely to be unreliably realized, making the electrically coupling between the semiconductor chip 10 and the substrate 20 to be unreliable.
Third, it would be difficult to provide a heat sink to the packaged semiconductor chip 10; and therefore, the finished flip-chip package would be low in heat-dissipation efficiency.
Fourth, since the semiconductor chip 10 is mounted over the front surface 20a of the substrate 20, the finished flip-chip package is considerably large in height.
Fifth, since the solder bumps 30 are spaced at quite a small pitch and unisolated from each other during the solder-reflow process, they can easily come in touch with adjacent ones when being melted during the solder-reflow process, resulting in short-circuiting between adjacent solder bumps.
Sixth, since the joint area between the semiconductor chip 10 and the substrate 20 is small (i.e., the semiconductor chip 10 only has its circuit surface 10a joined to the substrate 20), it would easily cause structural damage by thermal stress due to the CTE mismatch between the semiconductor chip 10 and the substrate 20.
Related patents, include, for example, the U.S. Pat. No. 5,742,100 entitled xe2x80x9cSTRUCTURE HAVING FLIP-CHIP CONNECTED SUBSTRATESxe2x80x9d. This patented technology discloses an inventive method for the fabrication of a flip-chip package. By this patented technology, however, the above-mentioned drawbacks still exist.
It is therefore an objective of this invention to provide a new flip-chip technology, which can be used to fabricate a flip-chip package without the necessity of solder-deflux and flip-chip underfill step so as to make the overall packaging process more simplified in procedural steps.
It is another objective of this invention to provide a new flip-chip technology, which can provide a larger solder-wetting area to help allow more reliable electrically coupling between the semiconductor chip and the substrate.
It is still another objective of this invention to provide a new flip-chip technology, which can help allow the finished flip-chip package to have an increased heat-dissipation efficiency.
It is yet another objective of this invention to provide a new flip-chip technology, which can provide a smaller package size than the prior art.
It is still yet another objective of this invention to provide a new flip-chip technology, which can help prevent the problem of short-circuiting between adjacent solder bumps during solder-reflow process.
It is still yet another objective of this invention to provide a new flip-chip technology, which can help allow the minimization of structural damage by thermal stress due to CTE mismatch between the semiconductor chip and the substrate.
In accordance with the foregoing and other objectives, the invention proposes a new flip-chip technology denominated as DDFC (Direct-Downset Flip-Chip) technology.
The DDFC technology according to the invention provides a new flip-chip packaging process, which, broadly recited, comprises the following steps (1) preparing a semiconductor chip and a substrate; the semiconductor chip having a circuit surface and a noncircuit surface, with the circuit surface being formed with an array of I/O pads; and the substrate having a front surface and a back surface, with the front surface being formed with a downset device hole and a plurality of recessed solder-bump pads of a predefined shape over the bottom surface of the device hole; (2) providing a plurality of solder bumps respectively over the I/O pads of the semiconductor chip; (3) embedding the semiconductor chip into the device hole, with the solder bumps being respectively fitted into the recessed solder-bump pads over the bottom surface of the device hole; (4) performing a solder-reflow process to reflow the solder bumps over the recessed solder-bump pads; and (5) performing a solder-ball implantation process to implant an array of solder balls over the back surface of the substrate.
The DDFC technology according to the invention provides a new flip-chip package assembly, which, broadly recited, comprises the following components: (a) a semiconductor chip having a circuit surface and a noncircuit surface, with an array of I/O pads being formed over the circuit surface thereof; (b) a plurality of solder bumps, which are respectively attached to the I/O pads on the semiconductor chip; (c) a substrate having a front surface and a back surface, with the front surface being formed with a downset device hole and a plurality of recessed solder-bump pads of a predefined shape corresponding to the solder bumps on the semiconductor chip; (d) an array of solder balls implanted over the back surface of the substrate; and (e) a heat sink mounted over the device hole and in contact with the semiconductor chip; wherein the semiconductor chip is embedded in a direct-downset manner in the device hole of the substrate, with the solder bumps being fitted within and reflowed over the recessed solder-bump pads over the bottom surface of the device hole.
The foregoing DDFC technology according to the invention has the following advantages over the prior art: (1) allows the flip-chip packaging process to be implemented without the necessity of solder-deflux and flip-chip underfill steps; (2) allows more reliable electrically coupling between the flip-chip and the substrate; (3) allows an increased heat-dissipation efficiency to the flip-chip package; (4) allows the package size to be made smaller in height; (5) allows the prevention of short-circuiting between adjacent solder bumps during solder-reflow process; and (6) allows the minimization of structural damage by thermal stress due to CTE mismatch between the semiconductor chip and the substrate. Owing to these benefits, the flip-chip technology of the invention is more advantageous to use than the prior art.